1. Field of the Invention
This invention generally relates to network communication systems, and more particularly to a network protocol handler architecture for processing and routing packets in high-traffic network environments.
2. Description of the Related Art
Conventional network protocol handlers are equipped with hardware that determines the processing functions to be performed on incoming packets. In operation, when a packet arrives from the network the hardware attached to the input port communicates packet arrival information to a processor which then performs protocol and/or routing actions. The processed packet is then sent to an output port for delivery to its intended destination. If the protocol handler acts as a router, the destination of a packet is another node in the network, and if the protocol handler is used as a network adapter, the destination of the packet is a host processor.
The hardware discussed above typically uses a direct memory access (DMA) circuit that receives incoming packets from an input port, writes the packet to memory, and then informs the network processor that a packet has been received. In conventional interfaces of this type, the informing step is implemented by either the DMA circuit raising an interrupt to controller or via a polling scheme. In this polling scheme, the DMA circuit sets a status word that is repeatedly read by the processor until a packet has actually been received.
To handle load requirements, high-traffic network interfaces can use a plurality of processors and/or threads to perform protocol functions. In a multiprocessor and/or multi-threaded environment, a packet has to be assigned to one of the plurality of processors. This task is often accomplished by one of the processors using one of several conventional assignment methods, such as table lookup, round-robin, or first come-first serve. These conventional packet assignment methods suffer from one or more of the following disadvantages:
â¢ High cost of determining handler processor/thread.
â¢ Random distribution of packets to processors/threads, which can lead to significant lock contention and therefore performance degradation.
â¢ Reordering of packets from a single sequence due to different processing latencies, which is the result of different load profiles of processors/threads.
â¢ Inefficient exploitation of the system attributable to uneven distribution of work among processors/threads.
In view of the foregoing considerations, it is apparent that a need exists for a system and method of improving packet handling in network interface equipment, and more specifically one which assigns packets to one of the processors/threads more efficiently by using a mapping function which keeps packet sequences intact when processed.